In recent years, a phase change memory using chalcogenide as a recording medium has been actively studied. The phase change memory is a kind of resistance change type memory that stores information by using the fact that the recording material between electrodes has a different resistive state.
The phase change memory stores information by using the fact that the resistivity of a phase change material such as Ge2Sb2Te5 is different between an amorphous state and a crystalline state. The resistance is higher in the amorphous state and lower in the crystalline state. Thus, information can be read from a memory cell by providing a voltage difference between both ends of an element, measuring a current flowing through the element, and determining a high resistive state/low resistive state of the element.
In the phase change memory, data is programmed/erased by changing electric resistance of a phase change film to different states by Joule heat generated by the current flowing through a phase change element. A reset operation, that is, an operation to change the phase change element to an amorphous state of higher resistance is performed by passing a large current for a short period to melt a phase change material and then rapidly reducing the current for cooling. On the other hand, a set operation, that is, an operation to change the phase change element to a crystalline state of lower resistance is performed by passing a current sufficient to retain the phase change material at temperature of crystallization for a long time. The phase change memory needs a smaller current to change the state of phase change film with a reducing memory cell size, which makes the phase change memory suitable in principle for the reduction of memory cell size. Therefore, the research thereof has been actively conducted.
PTL 1 below discloses, as a method of integrating a phase change memory, a configuration in which a plurality of through holes passing through all layers is formed by single patterning in a stacked structure in which a plurality of gate electrode materials and a plurality of insulator films are alternately stacked and a gate insulator film, a channel layer, and a phase change film are formed inside the through hole. An individual memory cell includes a cell transistor and a phase change element connected in parallel and a plurality of memory cells is connected in series in a vertical direction, that is, a normal direction of the semiconductor substrate to form a phase change memory chain. In an array configuration in PTL 1, an individual phase change memory chain is selected by a vertical type select transistor. A channel semiconductor layer of each select transistor has a structure isolated for each phase change memory chain.
A phase change memory can perform a reset operation at high speed due to features of the aforementioned set operation and reset operation, but compared therewith, a set operation is slower. As a technology to compensate for a challenge of slow speed of a set operation of the phase change memory, PTL 2 describes a method of performing a simultaneous set operation for a plurality of phase change memory chains that are physically adjacent to each other.
PTL 3 describes a configuration example that has a structure that makes it easier to drive a large current used for performing a reset operation by forming both of upper and lower electrodes of a chain cell into a plate shape and selects the chain by using multi-stage select transistors orthogonal to each other in a main surface of the semiconductor substrate.